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April 2017
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Consortium area
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Breaking News

 


  • ESSDERC Workshop on "III-V compound semiconductor technology and devices, for advanced nanoelectronics”

The joint workshop on “III-V compound semiconductor technology and devices for advanced nanoelectronics” was held on September 12, 2016 in Lausanne, in the framework of 
ESSDERC2016 (
http://esscirc-essderc2016.epfl.ch/home).

The workshop was jointly co-organized by the SINANO Institute and 2 successfull European projects III-V-MOS
and Compose3.


Presentations

 

  • IEDM, Dec 2015, Washington D.C: IBM Research reported for the first time the successful 3D monolithic (3DM) integration of hybrid CMOS inverters
 featuring a top InGaAs n-FET layer fabricated on a bottom SiGe p-FET layer, allowing independent device layer optimization. This collaboration extends on the
two VLSI 2015 papers from IBM Research on state-of-the-art InGaAs and SiGe FinFETs. The top InGaAs n-FETs, whose performance was optimized in the
framework of the EU projects III-V-MOS and COMPOSE3, are formed with a replacement-gate flow with high-k/metal gate (HKMG) and raised source/drain (RSD).
The bottom SiGe p-FETs feature sub-10 nm fins, HKMG and silicided RSD. In this demonstrator, the low InGaAs processing temperature is crucial to prevent NiSiGe
contacts degradation and maintain the excellent performance of the bottom p-FETs. This 3DM approach paves the way towards dense digital hybrid CMOS circuits
as well as system-on-chip where top InGaAs devices can act as high performance RF front-end over CMOS.
http://bit.ly/1Za6mZk

 

  • Joint Open Access publication

 A comprehensive study of band structure calculation methods for bulk and ultra thin InxGa1-xAs films and comparison with experimental ellipsometry bandgap data has been recently published by the consortium partners on Solid State Electronics DOI: 10.1016/j.sse.2015.09.005 . Consistently with the open strategic approach implemented by the project the publication is Open Access.

SSE

 

  • III-V-MOS 2nd Newsletter

2nd Newsletter