featuring a top InGaAs n-FET layer fabricated on a bottom SiGe p-FET layer, allowing independent device layer optimization. This collaboration extends on the
two VLSI 2015 papers from IBM Research on state-of-the-art InGaAs and SiGe FinFETs. The top InGaAs n-FETs, whose performance was optimized in the
framework of the EU projects III-V-MOS and COMPOSE3, are formed with a replacement-gate flow with high-k/metal gate (HKMG) and raised source/drain (RSD).
The bottom SiGe p-FETs feature sub-10 nm fins, HKMG and silicided RSD. In this demonstrator, the low InGaAs processing temperature is crucial to prevent NiSiGe
contacts degradation and maintain the excellent performance of the bottom p-FETs. This 3DM approach paves the way towards dense digital hybrid CMOS circuits
as well as system-on-chip where top InGaAs devices can act as high performance RF front-end over CMOS. http://bit.ly/1Za6mZk
A comprehensive study of band structure calculation methods for bulk and ultra thin InxGa1-xAs films and comparison with experimental ellipsometry bandgap data has been recently published by the consortium partners on Solid State Electronics DOI: 10.1016/j.sse.2015.09.005 . Consistently with the open strategic approach implemented by the project the publication is Open Access.