The III-V-MOS (Technology CAD for III-V Semiconductor-based MOSFETs) Project is a European Collaborative Project (2013-2016) funded by the European Commission under the 7th Framework Program.
Objective: Enabling fast and effective design of new transistors for high performance electronics and with greatly reduced power consumption.
Pr. Luca Selmi, Scientific Coordinator
IUNET, University of Udine
First III-V-MOS Workshop
The 1st Workshop on “III-V Semiconductor Materials in Nanoelectronics” will be held on January 26, 2015 morning, in Bologna, Italy in the framework of the First Joint International EUROSOI and ULIS Conference.
The workshop aims at presenting the state of the art of III-V compound semiconductors characterization, modeling and integration into mainstream CMOS technologies and to present recent advancements in industry-oriented TCAD software for III-V based devices. The workshop talks will have a tutorial