The III-V-MOS (Technology CAD for III-V Semiconductor-based MOSFETs) Project was a European Collaborative Project (2013-2016) funded by the European Commission under the 7th Framework Program.
Objective: Enabling fast and effective design of new transistors for high performance electronics and with greatly reduced power consumption.
The III-V-MOS project completed successfully on April 30th, 2017 but our activities will not stop here. Keep following us at major international conferences, via LinkedIn and via partner institution websites.
Pr. Luca Selmi, Scientific Coordinator
IUNET, University of Udine
Join our III-V-MOS LinkedIn Group here
The project logo ((c) III-V-MOS consortium) visually integrates a representation of the InAs valence and conduction band structure with the project name, to underline that rigorous band structure calculations are the starting point of any accurate modeling of nanoscale devices, and to highlight one of the important ingredients of the III-V-MOS project.